Digital and mixed signal circuits such as wireless communications devices often use clock signals. Phase lock loop (PLL) circuits and other locking circuits are used to compare a system clock with a reference clock source, and adjust the frequency of the system clock to ideally match or “lock” the system clock frequency with that of the reference clock source in a closed loop regulation. Such locking circuits typically include a PFD circuit, a charge pump, a loop filter and a voltage controlled oscillator (VCO) in a forward path, as well as a feedback circuit providing the oscillator output signal as feedback for comparison with the reference input by the PFD circuit. The PFD converts phase difference between the reference signal and the feedback signal to voltage pulses, which are used for pumping current into a loop filter to change the VCO control voltage. The PLL operates in a negative feedback, with the VCO output frequency changed so as to reduce the phase error between the reference signal and the VCO output signal.
In certain applications, the reference clock frequency will change (or a feedback divisor factor will change), requiring the PLL circuit to again acquire or lock to the updated reference signal. For example, portable electronic devices are often designed to operate at different or changing reference clock frequencies, and an output signal of a frequency synthesizer circuit employing a PLL may be unreliable during frequency switching. The frequency switching time the locking circuit takes to lock onto an updated reference clock signal is referred to as the lock time, and it is desirable to reduce the lock time. In general, the lock time depends on the PLL loop parameters.
Lock time can be reduced by changing loop filter parameters to adjust the loop bandwidth during frequency switching and by restoring the normal operating bandwidth when the PLL loop nears the locked condition. Another approach uses multiple charge pump circuits that are turned on or off depending on phase errors, where the charge pump current is reduced as the loop nears the locked condition. Other techniques modify a feedback divider value so that the phase error remains small all the time and a current is pumped into the loop filter using an auxiliary charge pump activated by a phase error monitor, where keeping the phase error small reduces ringing of the control voltage near the locked condition. However, these techniques involve additional analog circuitry and/or frequency lock detection circuitry.